1. Field of the Invention
This invention generally relates to an arrangement/method in which a semiconductor integrated circuit (IC) chip is mounted face-down directly on a circuit substrate to attain electric connection, and an electronic device using the same. More specifically, this invention relates to a unique and novel electrical connection arrangement/method for providing connection between a substrate (e.g., printed circuit board) and a flip-chip IC.
2. Description of Related Art
Although solder is frequently used for assembly of electronic devices, a quantity of connection terminals on IC packages has generally increased, while an IC package size has generally decreased. As a result, a pitch or spacing of terminals for an IC package has now decreased to a point (e.g., 130 .mu.m) where soldering technology is incapable of precisely providing solder to fine electrodes, so that assembly by soldering has become very difficult and/or unreliable in terms of product yield.
Thus, an alternative connecting technology for mounting a semiconductor IC directly on a substrate has been developed. More particularly, a flip-chip mounting method in which the semiconductor IC is mounted on the substrate with its active side facing down, has proven to be an effective arrangement/method to improve electrical characteristics and mounting density. For example, Japanese Examined Patent Publication No. Hei 6-66355 has disclosed a method in which projecting electrodes are formed on terminal electrodes of the semiconductor IC chip and a conductive adhesive agent is interposed b e tween contact points and electrodes on a substrate. Further, Japanese Examined Patent Publication No. Hei 8-2574369 has disclosed a method in which conductivity between conductive particles is intensified by hardening and shrinkage of resin filled between a semiconductor IC chip and circuit substrate of a flip-chip connecting structure, so as to enhance stability of electrical connection.
However, the aforementioned electrical connection using the conductive particles has such a serious problem in that electrical connecting resistances between the projecting electrodes of the semiconductor IC device and organic circuit substrate vary. Thus, a reliability level of each connecting point also varies, and therefore such arrangement is not suitable for increasing number of terminals and/or many applications.
Variation of the connecting resistance is considered to becaused partly by variation of a height of the projecting electrodes possessed by the semiconductor IC device, i.e., because of varying heights, the projecting electrodes have varying contact pressures with electrodes of a substrate. Thus, even if conductive paste is interposed between the projecting electrode and electrode, a sufficient connecting reliability cannot be obtained. Therefore, to suppress variation of the connecting resistance, it is important to suppress or compensate for variation of the height of the projecting electrodes. This is the same also when no conductive paste is interposed.
As a method for suppressing variation of the height of the projecting electrodes, there is a method in which when the semiconductor IC device is mounted on the substrate, pressure is applied to deform the projecting electrodes, substrate and/or substrate electrodes, and any variation is thus at tempted to be absorbed or compensated for by the deformation, e.g., as disclosed by Japanese Unexamined Patent Application No. Hei 8-111437 (hereinafter '437). However, to deform in the above manner, a pressure of 50 g/pin is needed, such that as more pins are provided, a greater overall pressure is required. Thus, a possibility that the semiconductor IC device and circuit substrate may be damaged increases. For example, when a semiconductor IC device having 200 pins is mounted, a pressure of 50.times.200 g=10 kg is needed. Currently available products cannot reliably bear such a pressure, and accordingly, results from the '437 reference tend to teach away from use of pressure. This is the same for products relatively easy to deform such as a product using a wire bump arrangement.
As further background, citation is also made to the following art of interest: Japanese Examined Patent Publication No. Hei 7-50726; Japanese Unexamined Patent Application No. Hei 9-107003; "A New Circuit Substrate For MCM-L", by Yusuke Wada, pp. 59-64, ICEMCM '95; "Flip Chip Mounting Using Stud Bumps And Adhesives For Encapsulation", by T. Kusagaya et al., pp. 238-246, ICEMM Proceedings '93; "Chip-On-Board Mounting Technology Using Stud-Bump-Bonding Technique", by Y. Tomura et al., pp. 90-97, National Technical Report Vol. 39, No. 2, April. 1993; "Advanced LSI Package Using Stud-Bump-Bonding Technology &lt;CSP (Chip Size Package&gt;", by Y. Nakamura et al., pp. 302-307, ICEMCM '95; "Simple Method For Flip-Chip Bonding On A Resin Substrate", by K. Matsuda et al., pp. 92-97, 1997 International Conference On Multichip Modules; "A Fine-Pitch Lead-Less-Chip Assembly Technology With The Built-Up PCB", by K. Tanaka, pp. 369-374, ICEMCM '96 Proceedings; "A Comparative Analysis Of High Density PWB Technologies", by J. G. Aday et al., pp. 239-244, ICEMCM '96 Proceedings.